The present invention relates to pads having metal and/or metal compound abrasives for planarizing microelectronic substrates in mechanical and chemical-mechanical planarizing processes.
Mechanical and chemical-mechanical planarizing processes (collectively xe2x80x9cCMPxe2x80x9d) are used in the manufacturing of microelectronic devices for forming a flat surface on semiconductor wafers, field emission displays and many other microelectronic-device substrates and substrate assemblies. FIG. 1 schematically illustrates a CMP machine 10 having a platen 20. The platen 20 supports a planarizing medium 40 that can include a polishing pad 41 having a planarizing surface 42 on which a planarizing liquid 43 is disposed. The polishing pad 41 may be a conventional polishing pad made from a continuous phase matrix material (e.g., polyurethane), or it may be a new generation fixed-abrasive polishing pad made from abrasive particles fixedly dispersed in a suspension medium. The planarizing liquid 43 may be a conventional CMP slurry with abrasive particles and chemicals that remove material from the wafer, or the planarizing liquid may be a planarizing solution without abrasive particles. In most CMP applications, conventional CMP slurries are used on conventional polishing pads, and planarizing solutions without abrasive particles are used on fixed abrasive polishing pads.
The CMP machine 10 can also include an underpad 25 attached to an upper surface 22 of the platen 20 and the lower surface of the polishing pad 41. A drive assembly 26 rotates the platen 20 (as indicated by arrow A), and/or it reciprocates the platen 20 back and forth (as indicated by arrow B). Because the polishing pad 41 is attached to the underpad 25, the polishing pad 41 moves with the platen 20.
A wafer carrier 30 is positioned adjacent the polishing pad 41 and has a lower surface 32 to which a substrate assembly 12 may be attached via suction. Alternatively, the substrate assembly 12 may be attached to a resilient pad 34 positioned between the substrate assembly 12 and the lower surface 32. The wafer carrier 30 may be a weighted, free-floating wafer carrier, or an actuator assembly 33 may be attached to the wafer carrier to impart axial and/or rotational motion (as indicated by arrows C and D, respectively).
To planarize the substrate assembly 12 with the CMP machine 10, the wafer carrier 30 presses the substrate assembly 12 face-downward against the polishing pad 41. While the face of the substrate assembly 12 presses against the polishing pad 41, at least one of the platen 20 or the wafer carrier 30 moves relative to the other to move the substrate assembly 12 across the planarizing surface 42. As the face of the substrate assembly 12 moves across the planarizing surface 42, material is continuously removed from the face of the substrate assembly 12.
CMP processes should consistently and accurately produce a uniformly planar surface on the substrate assembly to enable precise fabrication of circuits and photo-patterns. During the fabrication of transistors, contacts, interconnects and other features, many substrates develop large xe2x80x9cstep heightsxe2x80x9d that create a highly topographic surface across the substrate. Yet, as the density of integrated circuits increases, it is necessary to have a planar substrate surface at several stages of processing the substrate because non-uniform substrate surfaces significantly increase the difficulty of forming sub-micron features. For example, it is difficult to accurately focus photo-patterns to within tolerances approaching 0.1 xcexcm on non-uniform substrate surfaces because sub-micron photolithographic equipment generally has a very limited depth of field. Thus, CMP processes are often used to transform a topographical substrate surface into a highly uniform, planar substrate surface.
In the competitive semiconductor industry, it is also highly desirable to have a high yield in CMP processes by producing a uniformly planar surface at a desired endpoint on a substrate assembly as quickly as possible. For example, when a conductive layer on a substrate assembly is under-planarized in the formation of contacts or interconnects, many of these components may not be electrically isolated from one another because undesirable portions of the conductive layer may remain on the substrate over a dielectric layer. Additionally, when a substrate is over-planarized, components below the desired endpoint may be damaged or completely destroyed. Thus, to provide a high yield of operable microelectronic devices, CMP processing should quickly remove material until the desired endpoint is reached.
The planarity of the finished substrate assemblies and the yield of CMP processing is a function of several factors, one of which is the rate at which material is removed from the substrate assembly (the xe2x80x9cpolishing ratexe2x80x9d). Although it is desirable to have a high polishing rate to reduce the duration of each planarizing cycle, the polishing rate should be uniform across the substrate to produce a uniformly planar surface. The polishing rate should also be consistent to accurately endpoint CMP processing at a desired elevation in the substrate assembly. The polishing rate, therefore, should be controlled to provide accurate, reproducible results.
In manufacturing microelectronic substrate assemblies, metal features are typically incorporated into the substrate to electrically connect devices and features of the substrate. For example, metal plugs can extend between layers of the substrate assembly to connect portions of the layers, and metal interconnects can extend from one region of a layer to another to connect features on the same layer. The metal features can include a conductive element surrounded by a diffusion barrier, each formed from a different metal composition. During planarization, the material forming the conductive element typically planarizes at a faster rate than does the material forming the diffusion barrier. Accordingly, the conductive element can become xe2x80x9cdishedxe2x80x9d relative to the surrounding diffusion barrier, resulting in an uneven surface topography. As discussed above, an uneven surface typography can make it difficult to form sub-micron devices.
One approach to addressing this problem has been to add metal oxide abrasives to the planarizing liquid 43. For example, the planarizing liquid 43 can include titania abrasive particles to planarize a substrate assembly 12 having titania diffusion barriers or the planarizing liquid 43 can include alumina abrasive particles to planarize a substrate assembly 12 having alumina structures. However, this approach has several drawbacks as well. For example, the polishing rate can be influenced by the distribution of the planarizing liquid 43 between the substrate assembly 12 and the planarizing surface 42 of the polishing pad 41. The distribution of the planarizing liquid 43 may not be uniform across the surface of the substrate assembly 12 because the leading edge of the substrate assembly 12 can wipe a significant portion of the planarizing liquid 43 from the polishing pad 41 before the planarizing liquid 43 can contact the other areas of the substrate assembly. The non-uniform distribution of planarizing liquid 43 under the substrate assembly 12 can cause certain areas of the substrate assembly 12 to have a higher polishing rate than other areas because they have more contact with the chemicals and/or abrasive particles in the planarizing liquid 43. The surface of the substrate assembly 12 may accordingly not be uniformly planar, and in extreme cases, some devices may be damaged or destroyed by CMP processing.
The polishing rate may also vary from one substrate assembly to another, or even across a particular substrate, because the composition of the planarizing liquid 43 may vary. The chemicals added to the planarizing liquid 43 may degrade over time causing one batch of planarizing liquid 43 to have a different polishing rate than another batch of planarizing liquid 43. Additionally, many components in the planarizing liquid 43 settle in a liquid solution, and thus the concentration of chemicals of a particular batch of planarizing liquid 43 may also vary. As a result of the changes in the composition of the planarizing liquid 43, the polishing rate of a particular substrate assembly 12 may change, making it difficult to uniformly planarize the substrate assembly 12 and to stop the planarization at a desired endpoint.
Another conventional CMP method, used for planarizing a substrate having two different overlying metals, is to change the planarizing medium as the first metal is removed and the second metal is exposed. For example, the substrate can be moved from one polishing pad having an abrasivity 1o selected for removing the first metal to another polishing pad having a different abrasivity selected for removing the second metal, after the second metal is exposed. Alternatively, the chemical composition of the planarizing liquid can be changed as the second metal is exposed. In this way, the planarizing medium can be tailored to the particular metal being removed. This approach can have several drawbacks. For example, it can be time consuming to move the substrate from one polishing pad to another, or to change planarizing liquids, thereby reducing the efficiency of the CMP process. Furthermore, this approach may not satisfactorily remove the first and second metals when both metals are exposed simultaneously. Thus, conventional CMP processing may not provide sufficiently planar surfaces or an adequate yield of operable devices.
The present invention is directed toward methods and apparatuses for planarizing microelectronic substrates. In one aspect of the invention, the apparatus can include a fixed abrasive polishing pad having fixed abrasive elements that are selected to correspond to a metal in the microelectronic substrate. For example, where the microelectronic substrate includes a metal such as titanium, the polishing pad can include a compound of titanium, such as titanium dioxide. Alternatively, the polishing pad can include a refractory metal where the microelectronic substrate includes the same or a different refractory metal.
In another aspect of the invention, the apparatus can include the combination of a metal-containing microelectronic substrate and a fixed abrasive polishing pad. The substrate can have a metal feature with a first metal material and a second metal material adjacent to the first metal material. The fixed abrasive polishing pad can include a suspension medium having a plurality of abrasive elements that together have a first removal rate of the first metal material and a second removal rate of the second metal material such that a ratio of the first removal rate to the second removal rate is less than or equal to approximately two. The metal feature can include an interconnect located within a selected layer of the substrate, or it can include a conductive plug that extends between layers of the substrate.
In a method in accordance with still another aspect of the invention, a single planarizing liquid and a single polishing pad having fixed abrasive elements that include a metal compound can be engaged with a microelectronic substrate to remove metal material from the substrate. For example, where the substrate includes a substrate material with first and second metals, the second metal forming an interface with the substrate material and the first metal disposed on the second metal, the method can include engaging the substrate with the single polishing pad and the single planarizing liquid to remove both the first and second metals and expose the substrate material.